Chip Gallery


  • Process: 14 nm Intel CMOS process
  • Design: 32 Gbps 4-Channel Capacitive Proximity Communication Transceiver
  • Publication: ISSCC 2016, JSSC 2016
  • World's fastest and most-energy efficient mm-scale capacitive Proximity Communication Link



  • Process: 22 nm Intel CMOS process
  • Design25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter
  • Publication: ISSCC 2014

  • Process: 180 nm National Semiconductor process
  • DesignOrthogonally Tunable LNA for Zero-margin Receiver
  • Publication: ISCAS 2011, TCASI 2011 (special issue)
  • Orthogonally tunable LNA that allows independent control of Gain+NF or Linearity with power consumption. This enables dynamically extra power savings in RF receiver in both cases when SNR is high or interference is not present (VIZOR). 


  • Process: 22 nm Intel CMOS process
  • Design: 32Gb/s 3-Tap FFE/6-Tap DFE Bidirectional Serial Link Transceiver 
  • Publication: ISSCC 2014, JSSC 2014
  • Lowest-energy Scalable 4-32 Gbps Serial-link + Low-profile connector that impacted the design of USB-C type connector

  • Process: 65 nm TSMC CMOS process
  • DesignDVH-Receiver with Wideband Jammer Detector 
  • Publication: Shreyas Sen, Ph.D. Thesis, Georgia Tech, 2011
  • Wideband Jammer detector allowing programmable jammer detection time (5us to 6ms). This allows adaptive receiver power vs. performance trade-off when a jammer is not present 



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